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general description the hi-15530 is a high performance cmos integrated circuit designed to meet the requirements of mil-std-1553 and similar manchester ii encoded, time division multiplexed serial data protocols. the hi-15530 contains both an encoder and decoder, which operate independently. the hi-15530 is fully compatible with either 5v or 3.3v logic and transceivers. the device generates mil-std-1553 sync pulses, parity bits as well as the manchester ii encoding of the data bits. the decoder recognizes and identifies sync pulses, decodes data bits, and performs parity checking. the hi-15530 supports the 1mbit/s data rate of mil-std- 1553 over the full temperature and voltage range. for applications requiring small footprints and low cost, the hi-15530 is available in a 24-pin plastic ssop package. ceramic dip and lcc packages are also available to achieve the highest level of reliability and to provide drop-in replacements for obsolete parts from other manufacturers. applications mil-std-1553 interfaces smart munitions stores management sensor interfaces instrumentation features mil-std-1553 compatible interfaces to hi-1567 transceiver family 1.25 mbit/s maximum data rate 5v or 3.3v operation small footprint 24-pin plastic ssop package option direct replacement for: harris/intersil hd15530 gec plessey semiconductors mas15530 aeroflex act15530 manchester ii encode and decode sync identification and lock-in high temperature -55 c to +200 c option oo (ds15530 rev. k) 09/13 24 vdd 23 encoder clk 22 send clk in 21 send data 20 sync select 19 encoder enable 18 serial data in 17 16 15 14 6 out 13 master reset bipolar one out output inhibit bipolar zero out valid word 1 encoder shift clk 2 take data 3 serial data out 4 decoder clk 5 bipolar zero in 6 bipolar one in 7 unipolar data in 8 decoder shift clk 9 command / sync 10 decoder reset 11 gnd 12 data hi-15530psi hi-15530pst hi-15530psm pin configuration (top view) 24 pin ssop package (additional package pin configurations shown inside data sheet) 5v / 3.3v manchester encoder / decoder september 2013 hi-15530 holt integrated circuits www.holtic.com
signal section function description valid word decoder output a high output signals the receipt of a valid word encoder shift clock encoder output shifts data into the encoder on a low to high transition take data decoder output output is high during receipt of data after identification of a sync pulse and two valid manchester data bits. serial data out decoder output received data output in nrz format decoder clock decoder input 12x the data rate. clock for the transition finder and synchronizer, which generates the internal clock for the remainder of the decoder bipolar zero in decoder input a high input indicates the 1553 bus is in its negative state. this pin must be held high when the unipolar input is used bipolar one in decoder input a high input indicates the 1553 bus is in the positive state. this pin must be held low when the unipolar input is used unipolar data in decoder input input for unipolar data to the transition finder. must be held low when not in use decoder shift clock decoder output provides the decoder clock divided by 12, synchronized by the recovered serial data command / sync decoder output a high on this pin occurs during the output of decoded data which was preceded by a command (or status) synchronizing character. a low output indicates a data synchronizing character decoder reset decoder input a high applied to this pin during a decoder shift clock rising edge resets the bit counter gnd both power 0v supply master reset both input a high on this pin clears the 2:1 counters in both encoder and decoder and resets the divide-by-6 circuit 6 out encoder output provides encoder clock divided by 6 encoder output an active low output intended to drive the zero or negative sense of a mil-std-1553 line driver encoder input a low inhibits the and by forcing them to inactive high states encoder output an active low output intended to drive the one or positive sense on a mil-std-1553 line driver serial data in encoder input accepts serial data at the rate of the encoder shift clock encoder enable encoder input a high on this pin initiates the encode cycle. (subject to the preceeding cycle being complete) sync select encoder input actuates a command sync for an input high and a data sync for a low send data encoder output an active high output which enables the external source of serial data send clock in encoder input clock input at 2 times the data rate, usually driven by 6 out encoder clock encoder input input to the divide by 6 circuit. normal frequency is data rate x12 vdd both power 3.0 v to 5.5 v power supply pin data bipolar zero out output inhibit bipolar zero out bipolar one out bipolar one out pin descriptions hi-15530 holt integrated circuits 2
figure 2. encoder operation 01234567 1516171819 15 14 13 12 11 3 2 1 0 p 3210p 15 14 13 12 11 sync sync sync 15 14 13 12 11 3 2 1 0 10 sync valid (1) (2) (3) (4) (5) don?t care don?t care sync select encoder enable encoder shift clk send clk timing send data serial data in bipolar one out bipolar zero out bit counter character former master reset send clk in 6 out encoder clk send data encoder shift clk serial data in encoder enable sync select output inhibit bipolar one out bipolar zero out figure 1. encoder serial data in encoder enable figure 1. encoder to abort the encoder transmission a positive pulse must be applied at master reset. anytime after or during this pulse, a low to high transition on send clock clears the internal counters and initializes the encoder for a new word. the encoder requires a single clock with a frequency of twice the desired data rate applied at the send clock input. an auxiliary divide-by-six counter is provided on chip which can be utilized to produce the send clock by dividing the encoder clock. the encoder's cycle begins when encoder enable is high during a falling edge of encoder shift clock (1). this cycle lasts for one word length or twenty encoder shift clock periods. at the next low-to-high transition of the encoder shift clock, a high at sync select input actuates a command sync or a low will produce a data sync for that word (2). when the encoder is ready to accept data, the send data output will go high and remain high for sixteen encoder shift clock periods (3). during these sixteen periods the data should be clocked into the serial data in input with every low-to- high transition of the encoder shift clock (3) - (4). after the sync and the manchester ii coded data are transmitted through the and outputs, the encoder adds on an additional bit which is the parity for that word (5). if encoder enable is held high continuously, consecutive words will be encoded without an interframe gap. encoder enable must go low by time (5) as shown to prevent a consecutive word from being encoded. at any time a low on the input will force both bipolar outputs to a high state but will not affect the encoder in any other way. bipolar one bipolar zero output inhibit encoder operation hi-15530 holt integrated circuits 3
the decoder requires a single clock with a frequency of 12 times the desired data rate applied at the decoder clock input. the manchester ii coded data can be presented to the decoder in one of two ways. the bipolar one and bipolar zero inputs will accept data from a comparator sensed transformer coupled bus as specified in mil-std-1553. the unipolar data input can only accept non-inverted manchester ii coded data (e.g. from of an encoder). the decoder is free running and continuously monitors its data input lines for a valid sync character and two valid manchester data bits to start an output cycle. when a valid sync is recognized (1), the type of sync is indicated on command/ sync output. if the sync character was a command sync, this output will go high (2) and remain high for sixteen decoder shift clock periods (3), otherwise it will remain low. the take data output will go high and remain high (2) - (3) while the decoder is transmitting the decoded data through serial data out. the decoded data available at serial data out is in an nrz format. the decoder shift clock is provided so that the decoded bits can be shifted into an external register on every low-to-high transition of this clock (2) - (3). after all sixteen decoded bits have been transmitted (3) the data is checked for odd parity. a high on valid word output (4) indicates a successful reception of a word without any manchester or parity errors. at this time the decoder is bipolar zero out data hi-15530 decoder operation 01234567 16171819 15 14 13 12 11 2 1 0 p 210p 15 14 13 12 11 sync sync sync 15 14 13 12 3 2 1 0 sync (1) (2) (3) (4) may be high from previous reception valid word decoder shift clk timing take data serial data out bipolar one in biploar zero in figure 4. decoder operation 8 command / sync data 10 10 4 undefined looking for a new sync character to start another output sequence. valid word will go low approximately 20 decoder shift clock periods after it goes high if not reset low sooner by a valid sync and two valid manchester bits as shown (1). at any time in the above sequence, a high input on decoder reset during a low-to-high transition of decoder shift clock will abort transmission and initialize the decoder to start looking for a new sync character. take data unipolar data in bipolar one in bipolar zero in master reset decoder clk decoder reset command/ sync data serial data out valid word decoder shift clk transition finder character identifier synchronizer bit counter bit rate clk parity check figure 3. decoder holt integrated circuits 4
hi-15530 timing diagrams command / sync data serial data out t d6 decoder timing t d7 take data t d8 decoder shift clk decoder shift clk data bit command / sync data t d9 t d10 take data decoder shift clk t d11 valid word t drh t drs decoder shift clk t dr decoder reset encoder shift clk serial data in send clk send clk encoder enable send data send clk encoder shift clk sync select encoder shift clk bipolar one out bipolar zero out or valid t e1 t e2 t e1 t e4 t e5 t e6 t e7 t e8 t e9 encoder timing valid t e3 valid holt integrated circuits 5
hi-15530 timing diagrams (cont.) mil-std-1553 word formats 012345678910 12 11 13 14 15 16 17 18 19 bit period command word data word status word r/t subaddress / mode data word count p p p data word terminal address me code for failure modes terminal address sync sync sync sync sync sync tf bipolar zero in t d2 decoder timing bipolar one in bit period bit period bit period t d1 t d1 t d3 t d3 bipolar zero in t d2 bipolar one in t d1 t d1 t d3 t d3 t d2 bipolar zero in bipolar one in t d1 t d3 t d3 t d1 t d4 t d3 t d1 t d3 t d5 t d5 t d4 t d1 t d3 unipolar in unipolar in unipolar in t d2 t d4 t d4 t d2 t d2 t d2 t d5 t d4 t d5 t d2 command sync data sync zero one one zero one one command sync data sync holt integrated circuits 6
hi-15530 v = 3.0 v to 5.5 v, gnd = 0v, ta = operating temperature range (unless otherwise specified). dd absolute maximum ratings note: stresses above those listed under "absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is n ot implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. dc electrical characteristics limits parameter conditions unit symbol input voltage input voltage hi v 70% v v input voltage lo vil 30% v v clock input voltage input voltage hi v v -0.5 v input voltage lo v 0.5v v input leakage current input sink i 1.0 input source i -1.0 min typ max ih dd dd ihc dd ilc ih a a output voltage logic ?1? output voltage v v =5v10%, i =-3ma 2.4 v v v =3.3v10%, i =-1ma 90% v v logic ?0? output voltage v v =5v10%, i =1.8ma 0.4 v v v =3.3v10%, i =1ma 10% v v standby supply current i v =v , outputs open 2.0 ma operating supply current i f=1mhz, outputs open 10.0 ma input capacitance c 7.0 pf output capacitance c 10.0 pf il oh1 dd oh oh2 dd oh dd ol1 dd ol ol2 dd oh dd ddsb in dd dd in out power dissipation at 25c plastic ssop 1.5 w, derate10mw/ c ceramic dip 1.0 w, derate 7mw/ dc current drain per pin 10ma c storage temperature range: -65c to +150c supply voltage v -0.3v to +7v v dd oltage at any pin -0.3v to vcc +0.3v operating temperature range: industrial -40c to +85c extended -55c to +125c hi-temp -55c to +200c holt integrated circuits 7
hi-15530 ac electrical characteristics vdd = 3.0v to 5.5v, gnd = 0v, ta = operating temperature range, cl=50pf limits parameter symbol units min typ max encoder timing decoder timing encoder clock frequency fec 0 15 mhz send clock frequency fesc 0 2.5 mhz encoder clock rise time tecr 8 ns encoder clock fall time tecf 8 ns encoder data rate fed 0 1.25 mhz master reset pulse width tmr 150 ns shift clock delay te1 125 ns serial data setup time te2 75 ns serial data hold time te3 75 ns enable setup time te4 90 ns enable pulse width te5 80 ns sync setup time te6 55 ns sync pulse width te7 150 ns send data delay te8 0 50 ns bipolar output delay te9 130 ns enable hold time te10 10 ns sync hold time te11 95 ns decoder clock frequency fdc 0 15 mhz decoder clock rise time tdcr 8 ns decoder clock fall time tdcf 8 ns decoder data rate fdd 0 1.25 mhz decoder reset pulse width tdr 150 ns decoder reset setup time tdrs 75 ns decoder reset hold time master reset pulse width tmr 150 ns bipolar data pulse width td1 tdc+10 ns sync transition span td2 18tdc ns one-zero overlap td3 tdc-10 ns short data transition span td4 6tdc ns long data transition span td5 12tdc ns sync delay (on) td6 -20 110 ns take data delay (on) td7 0 110 ns serial data out delay td8 80 ns sync delay (off) td9 0 110 ns take data delay (off) td10 0 110 ns valid word delay td11 0 110 ns tdrh 10 ns holt integrated circuits 8
hi-15530 additional pin configurations (see data sheet page 1 for 24-pin small outline ssop) 28 - pin ceramic lcc 4 3 2 1 28 27 26 12 13 14 15 16 17 18 5 6 7 8 9 10 11 25 24 23 22 21 20 19 send data n/c n/c sync select encoder enable serial data in bipolar one out decoder clk n/c n/c bipolar zero in bipolar one in unipolar data in decoder shift clock serial data out take da ta encoder shift clk valid word vdd encoder clk send clk in command / sync decoder reset gnd master reset data bipolar zero out output inhibit 6 out hi-15530cli hi-15530clt hi-15530clm valid word 1 encoder shift clk 2 take data 3 serial data out 4 decoder clk 5 bipolar zero in 6 bipolar one in 7 unipolar data in 8 decoder shift clk 9 command / sync 10 decoder reset 11 gnd 12 data 24 vdd 23 encoder clk 22 send clk in 21 send data 20 sync select 19 encoder enable 18 serial data in 17 16 15 14 6 out 13 master reset bipolar one out output inhibit bipolar zero out 24 - pin ceramic side-brazed dip hi-15530cdi hi-15530cdt hi-15530cdm ordering information hi - (plastic) 15530ps x x package description 24 pin plastic ssop (24hs) part number 15530ps lead finish part number 100% matte tin (pb-free, rohs compliant) f blank tin / lead (sn / pb) solder temperature range flow burn in -40c to +85c no i -55c to +125c no t part number t i -55c to +125c yes m m see next page for ceramic package style ordering information holt integrated circuits 9
ordering information (cont.) hi-15530 holt integrated circuits 10 -55c to +200c no h h hi - (ceramic) 15530cx x temperature range flow burn in -40c to +85c no i -55c to +125c no t part number t i -55c to +125c yes m m tin / lead (sn / pb) solder lead finish gold (pb-free, rohs compliant) gold (pb-free, rohs compliant) part number package description 24 pin ceramic side brazed dip (24c) 28 pin ceramic leadless chip carrier (28s) 15530cd 15530cl gold (pb-free, rohs compliant), dip only
revision history hi-15530 revision date description of change ds15530 rev. j 10/16/08 corrected package height i for 24-pin ceramic side-brazed dip and clarified temperature ranges. rev. k 09/18/13 added hi-15530cdh high temperature option. n package dimension drawing holt integrated circuits 11
hi-15530 package dimensions 24-pin ceramic side-brazed dip inches (millimeters) package type: 24c bsc = ?basic spacing between centers? is theoretical true position dimension and has no tolerance. (jedec standard 95) 1.220 .085 .009 (2.159 .229) .610 .010 (15.494 .254) .600 .010 (15.240 .254) .595 .010 (15.113 .254) .010 .002 .001 (.254 .051 .025) .100 (2.54) bsc (30.988) max .200 (5.080) max .125 (3.175) min .018 (.457) typ .050 (1.270) typ 24-pin plastic ssop inches (millimeters) package type: 24hs bsc = ?basic spacing between centers? is theoretical true position dimension and has no tolerance. (jedec standard 95) .307 .016 (7.80 .40) .209 .012 (5.30 .30) 0 to 8 .005 .001 (0.13 .08) typ .323 .012 (8.20 .30) .030 .008 (0.75 .20) .073 .0055 (1.86 .14) .012 (.30) see detail a detail a .026 (.650) bsc typ .06 (0.15) holt integrated circuits 12
hi-15530 package dimensions 28-pin ceramic leadless chip carrier inches (millimeters) package type: 28s bsc = ?basic spacing between centers? is theoretical true position dimension and has no tolerance. (jedec standard 95) .451 .009 (11.455 .229) sq. .080 .020 (2.032 .508) .040 x 45 3pls (1.016 x 45 3pls) .050 .005 (1.270 .127) .025 .003 (.635 .076) pin 1 .008r .006 (.203r .152) pin 1 .050 (1.270) bsc .020 (.508) index holt integrated circuits 13

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